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lpm_shiftreg(2)
- shift register with Quartus -shift register with Quartus II
ddr-sdram-verilog-resource
- 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-descr iption the resource code of ddr_sram
license
- 这是一个QUARTUS II的破解文件，用TEXT打开方式打开，将里面的ID地址换成你所用的电脑ID即可！-This is a QUARTUS II of crack file, TEXT Open Open, will be replaced inside the ID address of the computer ID you can use!
tutorial
- quartus ii 6.0版本tutorial文件，在不同的版本中会出现不同的说明介绍，包括6.0/ 7.2/ 8.0。-tutorial for quartus ii 6.0 that illustrate a quiker way to get access of basic feature of the design software
tiaopin
- 开题报告，基于Quartus ii的DDS设计和实现。-Opening report, based on Quartus ii of DDS design and implementation.
sopcIIC
- 该例子是基于sopc的IIC总线设计完整设计，分为硬件和软件部分，软件部分是用c语言编写的。该项目是个以完成的项目，据有较高的参考和经济价值。该例子是原来做过的项目。 整个项目是在Quartus II 7.0和nios IDE环境下开发。-This example is based on the IIC bus design sopc complete design, divided into hardware and software, the software part is writt
0608190248xiatao
- 实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。 关键字：数字钟 闹钟 仿真 准点报时 -Quartus II software by means of experimental Lee designed a multi-functional digital clock and real
100516
- Quartus II 中Signaltap 的使用教程 -Quartus II tutorial in the use of Signaltap
lcd
- 128*64点阵液晶显示控制器时钟模块，quartus II 运行-128* 64 dot matrix LCD controller clock module, quartus II run
verilog-vga
- Verilgo编写的VGA显示接口示例程序, 在显示器上显示矩形彩条, 包含Quartus II 8.1工程文件及VGA的相当资料(PDF及WORD文档)-Verilgo prepared VGA display interface sample program, the color of the rectangle on the display, including the Quartus II 8.1 project file and VGA considerable data (PDF a
LCD12864
- LCD12864显示 verilog hdl编译已通过 编译器 Quartus II 9.0sp2 所有文件已包含-LCD12864 Show verilog hdl compiler has compiler Quartus II 9.0sp2 through all the files included
2BCD
- 二进制转BCD码 verilog hdl Quartus II 9.0sp2 编译通过 所有的文件-Binary to BCD code verilog hdl Quartus II 9.0sp2 compile all the documents
I2C
- 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：modelsim 综合工具：quartus -Language:
danzhouqiCPU
- VHDL单周期CPU设计,基于Quartus II 开发平台-VHDL single-cycle CPU design, Quartus II development platform based on
stratixIII_3sl150_dev_TSE_SGMII_v1
- 该程序实现altera开发板 stratix III 3S150通过以太网与pc之间通信。 使用Quartus II和Nios II 设计。 因为altera官方没有这块板子的正确网卡与pc通信的程序，-Overall This example works at 1000M/100M/10M Base SGMII mode on SIII 3S150 Kit. Designed by Quartus II/IP Cores/Nios II EDS v8.0 This is not
TEST5
- 8位硬件加法器设计 熟悉Quartus II的VHDL文本设计流程全过程，学习简单时序电路的设计、仿真和测试。-eight bit Hardware adder design Familiar with Quartus II VHDL text design flow process, learn the simple sequential circuits design, simulation and testing
serial_adder
- This is a simple Serial Adder for Quartus II. The source code is in verilog HDL
Quartus-II
- Altera® Quartus® II 设计软件是用于可编程片上系统 (SOPC) 的最全面的设 计环境。-Altera ® Quartus ® II design software is used for system-on-programmable chip (SOPC) the most comprehensive design environment.
Quartus_Modelsim_setup
- communication between quartus II and modelsim altera
SDRAMPNIOS-II
- 带SDRAM的nios II系统，开发环境为Quartus II 9.0 + Nios II 9.0-With the nios II SDRAM system, development environment for the Quartus II 9.0+ Nios II 9.0